The present invention relates to method for fabricating a memory device. In particular, the present invention relates to a method for fabricating a semiconductor device wherein a buried insulating film is formed under a gate to form a SOI (Silicon-on-Insulator) channel region, thereby reducing a short channel effect and junction leakage current of the device.
FIGS. 1a through 1e are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1a, a pad oxide film 13 and a pad nitride film 15 are formed over a semiconductor substrate 10. The pad nitride film 15, the pad oxide film 13 and the semiconductor substrate 10 are etched by a predetermined thickness to form a trench 20.
Referring to FIGS. 1b and 1c, an insulating film for device isolation (not shown) filling up the trench 20 is formed. Next, the insulating film for device isolation is polished until the pad nitride film 15 is exposed to form a device isolation structure 30 defining an active region. Thereafter, the pad nitride film 15 is removed.
Referring to FIGS. 1d and 1e, a process for implanting impurity ions 33 is performed on the entire surface to form a well and channel ion implantation region (not shown) in the semiconductor substrate 10. The pad oxide film 13 is removed to expose the semiconductor substrate 10. Next, a gate insulating film 60 is formed over the exposed semiconductor substrate 10. A gate conductive layer (not shown) and a hard mask layer (not shown) are formed over the entire surface of the resultant. Thereafter, the hard mask layer and the gate conductive layer are etched using a gate mask (not shown) to form a gate 90 having a stacked structure of a gate electrode 70 and a hard mask layer pattern 80.
According to the above method for fabricating a semiconductor device, it is difficult to lower a threshold voltage because the channel length is decreased according the shrunk design rule. Since the width between the gates is decreased, a short channel effect is also advanced. In particular, as voltage of a drain region is increased, the electrical potential barrier at a source region is lowered due to interaction of the drain region with the active region, thereby increasing DIBL (Drain Induced Barrier Lowering) effect. Accordingly, the gate voltage cannot control the drain voltage, and in a worse case their depletion regions are encountered. As a result, electrons are driven toward the drain region due to high electric field between the source region and the drain region. In order to maintain threshold voltage of the device according to the decreased width of the gate, ion-doped concentration of the channel region is increased. For controlling a “punch-through” phenomena, impurity ions are implanted in the channel region to relatively increase the electric field of the junction region. Accordingly, the refresh character of the device is degraded.